1. Field of the Invention
The present invention relates to a method for fabricating a high tensile stress film, and more particularly, to a method for fabricating a high tensile stress film on a strained-silicon Metal-Oxide-Semiconductor (MOS) transistor.
2. Description of the Prior Art
As semiconductor processes advance to very deep sub-micron geometries, such as 65-nm node and beyond, and with the progress of device miniaturization, enhancing carrier mobility and a driving current of a Metal-Oxide-Semiconductor (MOS) transistor has become a critical issue. In order to improve a speed of the MOS transistors, a strained-silicon technique has been developed and is taken as a main solution to improve performance of the MOS transistor. This technique improves scaling limits and device performance by introducing strain into the channel region, which can improve electron and hole mobility.
In one approach of the strained-silicon technique, a high stress film, such as a poly stressor or a contact etch stop layer (CESL), is formed over the MOS transistors to provide stress; in another approach, devices are fabricated directly on a strained-silicon wafer incorporating selective epitaxial growth (SEG). The former described approach is additionally divided into two branches according to different electrical demands for PMOS and NMOS: a high tensile stress film providing a uniaxial tensile stress on a source/drain and a channel region of an NMOS improves electron mobility, whereas a high compressive stress film providing a uniaxial compressive stress on a source/drain and a channel region of a PMOS improves hole mobility.
Please refer to FIG. 1, which is a schematic drawing illustrating a conventional method for fabricating a high tensile stress film. As shown in FIG. 1, a semiconductor substrate 10 comprises at least an NMOS transistor 12, which includes a gate structure. The gate structure comprises a gate oxide 14 and a gate 16 formed on the gate oxide 14. A cap layer 18 is formed on top of the gate 16 and an ONO offset spacer 20 is formed on sidewalls of the gate structure. In addition, the NMOS transistor 12 further comprises source/drain regions 22. Shallow trench isolations (STIs) 24 around the NMOS transistor 12 are formed in the semiconductor substrate 10. Please refer to FIG. 1 again. A high tensile stress film 26 composed of silicon nitride or silicon oxide is formed on a surface of the NMOS transistor 12 by a plasma-enhanced chemical vapor deposition (PECVD) method.
Generally speaking, the tensile-stress status of the high tensile stress film 26 has to be greater than 1.5 GPa, and it is required to be greater than 1.8 GPa in a next-generation 45 nm process. However, so far 1.5 GPa is an upper performance limit for the high tensile stress film formed by the conventional PECVD method. Therefore, the prior art provides a rapid thermal processing (RTP) method, which applies a high temperature, such as 1000° C., to the high tensile stress film 26 to adjust its tensile stress status. However, the RTP method is limited when applied to a CESL, which is formed on a substrate having a silicide layer over gate and source/drain regions, because the silicide layer may be destroyed at such a high temperature. To avoid this problem, the temperature of the RTP method is reduced, but accordingly the target value of the tensile-stress status is reduced.
Furthermore, the prior art also provides an ultra violet (UV) curing method to adjust the tensile stress status of the high tensile stress film 26 by exposing the high tensile stress film 26 to a UV light. The UV curing method utilizes photons to break the Si—H and SiN—H bonds of the high tensile stress film 26 and removes hydrogen from the high tensile stress film 26. Thus, an irreversible tensile stress is generated in the high tensile stress film 26. In other words, the more hydrogen is removed, the higher the tensile stress status of the high tensile stress film 26 is obtained. However, the UV curing method requires a longer process period and is limited by a thickness of the high tensile stress film 26.